About

A minimal portfolio demonstrating the intersection of electronic systems, financial algorithms, and embedded AI—where hardware‑accelerated inference meets real‑time data feeds.

My foundation in ECE spans signal integrity, timing analysis, RTL design, and hardware‑software co‑design. That expertise informs every project I build with deterministic performance and tight resource budgets.

I architect low‑latency order‑book engines, quantitative back‑tests, and custom inference pipelines in C++, Rust, and Python—owning critical paths from bit‑level optimizations through high‑throughput APIs.

Financial models become hardware‑friendly algorithms via bespoke quantization toolchains and transformer accelerators. Machine learning, FPGA IP, and real‑time observability converge to deliver production‑grade systems.

I’m continuously iterating on an FPGA‑based transformer core, a sub‑watt microcontroller inference runtime, and high‑frequency simulation frameworks. Explore the full technical breakdown here.